A Proposed Cache Line Implementation Solution with Error/correcting Capabilities for Managing Cache Coherency in Multiprocessor Systems
نویسنده
چکیده
The paper presents a solution for designing a cache coherency state machine for a multiprocessor system with error/correcting capabilities for the unidirectional errors and the used resources implied by a FPGA implementation of our solution. The cache coherency method used is based on the MESI protocol. The implementation is realized with FPGA by using the ALTERA Program.
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